Part Number
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IS61DDB41M18A |
Manufacturer
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Integrated Silicon Solution |
Description
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18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM |
Published
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Jul 25, 2016 |
Detailed Description
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IS61DDB41M18A IS61DDB451236A
1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
ADVANCED INFORMATION JULY 2012
...
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Datasheet
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IS61DDB41M18A
|
Overview
IS61DDB41M18A IS61DDB451236A
1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
ADVANCED INFORMATION JULY 2012
FEATURES
DESCRIPTION
512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two input clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
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