Part Number
|
IS61DDPB21M36B1 |
Manufacturer
|
Integrated Silicon Solution |
Description
|
36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM |
Published
|
Jul 25, 2016 |
Detailed Description
|
IS61DDPB22M18B/B1/B2 IS61DDPB21M36B/B1/B2
2Mx18, 1Mx36 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latenc...
|
Datasheet
|
IS61DDPB21M36B1
|
Overview
IS61DDPB22M18B/B1/B2 IS61DDPB21M36B/B1/B2
2Mx18, 1Mx36 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.
5 Cycle Read Latency)
SEPTEMBER 2014
FEATURES
DESCRIPTION
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.
5 cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
...
Similar Datasheet