36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB22M18A/A1/A2 IS61DDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-tim...
Integrated Silicon Solution