IS43R83200F IS43/46R16160F, IS43/46R32800F 8Mx32, 16Mx16, 32Mx8 PRELIMINARY INFORMATION 256Mb DDR SDRAM MARCH 2014 FEATURES DEVICE OVERVIEW • VDD and VDDQ: 2.
5V ± 0.
2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurre...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)