CDP1881C, CDP1882, CDP1882C March 1997 CMOS 6-Bit Latch and Decoder Memory Interfaces Description The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit memory latch and decoder circuits intended for use in CDP1800 series microprocessor systems.
They can interface directly with the multiplexed address bus of this system at maximum clock frequency, and up to four 4K x 8-bit memories to provide a 16K byte memory system.
With four 2K x 8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed address bus microprocessors.
By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general purpose ...

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