Data Sheet High Performance, 3.
2 GHz, 14-Output Fanout Buffer HMC7043 FEATURES JEDEC JESD204B support Low additive jitter: 15 fs rms at 2457.
6 MHz (12 kHz to 20 MHz) Very low noise floor: −155.
2 dBc/Hz at 983.
04 MHz Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz JESD204B-compatible system reference (SYSREF) pulses 25 ps analog and ½ clock input cycle digital delay independently programmable on each of 14 clock output channels SPI-programmable adjustable noise floor vs.
power consumption SYSREF valid interrupt to simplify JESD204B synchronization Supports deterministic synchronization of multiple HMC7043 devices ...

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