Part Number
|
CY7C1263V18 |
Manufacturer
|
Cypress Semiconductor |
Description
|
1.8V Synchronous Pipelined SRAM |
Published
|
Nov 6, 2016 |
Detailed Description
|
CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18
36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latenc...
|
Datasheet
|
CY7C1263V18
|
Overview
CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18
36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.
5 Cycle Read Latency)
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.
5 clock cycles ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Single multiplexed address input bus latches address inputs
for both read and write ports ■ ...
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