Part Number
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CY7C1306BV18 |
Manufacturer
|
Cypress Semiconductor |
Description
|
18-Mbit Burst of 2 Pipelined SRAM |
Published
|
Nov 6, 2016 |
Detailed Description
|
CY7C1303BV18 CY7C1306BV18
18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
•...
|
Datasheet
|
CY7C1306BV18
|
Overview
CY7C1303BV18 CY7C1306BV18
18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports — Supports concurrent transactions
• 167-MHz Clock for high bandwidth — 2.
5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports • Separate Port Selec...
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