PL500-15

FE AT UR E S PL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) PIN CONFIGURATION  VCXO with Divider Selection (DIVSEL) input pin  PL500-15: ÷8, ÷16  PL500-16: ÷2, ÷4  VCXO output for the 1MHz to 18MHz range  16MHz to 36MHz fundamental crystal input.  Low phase noise (-130 dBc @ 10kHz offset using a 35.328MHz crystal).  LVCMOS output with OE tri-state...