Si5316
PRECISION CLOCK JITTER ATTENUATOR
Features
Fixed frequency jitter attenuator Dual clock inputs with integrated
with selectable clock ranges at
clock select mux
19, 38, 77, 155, 311, and 622 MHz (710 MHz max)
One clock input can be 1x, 4x, or 32x the frequency of the second
Support for SONET, 10GbE,
clock input
10GFC, and corresponding FEC Single clock output with
rates
selectable signal format:
Ultra-low jitter clock output with LVPECL, LVDS, CML, CMOS
jitter generation as low as 0.
3 psRMS (50 kHz–80 MHz)
LOL, LOS alarm outputs Pin programmable settings
Integrated loop filter with selectable loop bandwidth (100 Hz–7.
9 kHz)
On-chip voltage
regulator...