CD4029BMS December 1992 CMOS Presettable Up/Down Counter Description CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes.
The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals.
Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock.
A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count.
The counter is advanced one count at the positive transition of th...

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