CD4033BMS December 1992 CMOS Decade Counter/Divider Description CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display.
This device is particularly advantageous in display applications where low power dissipation and/or low package count is important.
A high RESET signal clears the decade counter to its zero count.
The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low.
Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high.
The CLOCK INHIBIT signal can be used as a negative-e...

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