eorex EM44CM1688LBA 1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.
8V ± 0.
1V.
• All inputs and outputs are compatible with SSTL_18 interface.
• Fully differential clock inputs (CK,/CK) operation.
• 8 Banks • Posted CAS • Burst Length: 4 and 8.
• Programmable CAS Latency (CL): 3, 4 and 5.
• Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) • Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition wi...

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