Revision History Revision 0.
1 (Mar.
2012) -First release.
Revision 0.
2 (Oct.
2013) -Add package size.
EM47EM1688SBB Oct.
2013 1/39 www.
eorex.
com EM47EM1688SBB 4Gb (32M×8Bank×16) Double DATA RATE 3 SDRAM Features • JEDEC Standard VDD/VDDQ = 1.
5V±0.
075V.
• All inputs and outputs are compatible with SSTL_15 interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks • Posted CAS by programmable additive latency • Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5,6,7,8 • CAS Latency (CL): 6,7,8,9,10,11 • Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs...

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