Revision History Revision 0.
1 (Jun.
2012) - First release.
EM48BM1684LBC Jun.
2012 www.
eorex.
com 1/20 EM48BM1684LBC 512Mb (8M4Bank16) Mobile Synchronous DRAM Features • Fully Synchronous to Positive Clock Edge • VDD= 1.
7 ~1.
95V for 133/166MHz Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • All Inputs are sampled at the Rising Edge of the System Clock • Auto Refresh and Self Refresh • 8,192 Refre...

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