DATA SHEET 128M bits DDR SDRAM EDD1232ABBH (4M words × 32 bits) Specifications • Density: 128M bits • Organization ⎯ 1M words × 32 bits × 4 banks • Package: 144-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.
5V ± 0.
125V • Data rate: 400Mbps (max.
) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 3 • Precharge: auto precharge operation for each burst access • Driver strength: weak/matched • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/32ms ⎯ Average refresh period: 7.
8μs • Operating ambient temperature range ⎯ TA = ...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)