CD4512BMS December 1992 CMOS Dual 4-Bit Latch Pinout CD4512BMS TOP VIEW D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 VSS 8 16 VDD 15 3-STATE DISABLE 14 SEL.
OUTPUT 13 C 12 B 11 A 10 INHIBIT 9 D7 Features • High-Voltage Types (20-Volt Rating) • 3-State Outputs • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.
5V at VDD = 15V • Meets all Requirements of JEDEC Tentative Standard No.
13B, "Standard Specifications for Description of ‘B’ Series...

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