Data Sheet FEATURES Ultralow noise floor: −165.
9 dBc/Hz or −165.
2 dBc/Hz (LVPECL or LVDS) at 2000 MHz Configurable to LVPECL or pseudo LVDS outputs 2.
5 V or 3.
3 V LVPECL operation (LVDS 2.
5 V only) Wideband: 10 MHz to 3500 MHz operating frequency range Flexible input interface LVPECL, LVDS, CML, and CMOS compatible AC or dc coupling On-chip 50 kΩ pull-up/pull-down resistors to VDD and GND Multiple output drivers Up to 8 differential or 16 single-ended LVPECL or LVDS outputs Low speed digital control via the IN_SEL and CONFIG pins 28-lead, 5 mm × 5 mm, LFCSP package, 25 mm2 APPLICATIONS SONET, Fibre Channel, GigE clock distribution ADC/DAC clock distribution Low skew and jitter clocks Wireles...

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