Part Number
|
CY7C1268KV18 |
Manufacturer
|
Cypress Semiconductor |
Description
|
36-Mbit DDR II+ SRAM Two-Word Burst Architecture |
Published
|
Mar 14, 2017 |
Detailed Description
|
CY7C1268KV18/CY7C1270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRA...
|
Datasheet
|
CY7C1268KV18
|
Overview
CY7C1268KV18/CY7C1270KV18
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency)
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.
5 Cycle Read Latency)
Features
■ 36-Mbit density (2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
1100 MHz) at 550 MHz ■ Available in 2.
5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operate...
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