Part Number
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CY7C2165KV18 |
Manufacturer
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Cypress Semiconductor |
Description
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18-Mbit QDR II+ SRAM Four-Word Burst Architecture |
Published
|
Mar 14, 2017 |
Detailed Description
|
CY7C2163KV18/CY7C2165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit ...
|
Datasheet
|
CY7C2165KV18
|
Overview
CY7C2163KV18/CY7C2165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.
5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
■ Available in 2.
5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Data valid pin (QVL...
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