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CY7C2642KV18

144-Mbit QDR II+ SRAM Two-Word Burst Architecture

Description

CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing addr...


Cypress Semiconductor

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