MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad OR/NOR Gate The MC10101 is a quad 2–input OR/NOR gate with one input from each gate common to pin 12.
PD = 25 mW typ/gate (No Load) tpd = 2.
0 ns typ tr, tf = 2.
0 ns typ (20%–80%) LOGIC DIAGRAM 42 5 73 6 10 14 11 13 15 12 9 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 MC10101 L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 DIP PIN ASSIGNMENT VCC1 AOUT BOUT AIN AOUT BOUT BIN VEE 1 2 3 4 5 6 7 8 16 VCC2 15 DOUT 14 COUT 13 DIN COMMON 12 INPUT 11 COUT 10 CIN 9 DOUT Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 6–36 of the Motorola MECL Data ...

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