Philips Semiconductors
Product specification
PowerMOS
transistor Voltage clamped logic level FET
GENERAL DESCRIPTION
Protected N-channel enhancement mode logic level field-effect power
transistor in a plastic envelope suitable for surface mount applications.
The device is intended for use in automotive applications.
It has built-in zener diodes providing active drain voltage clamping.
BUK563-48C
QUICK REFERENCE DATA
SYMBOL V(CL)DSR ID Ptot Tj WDSRR RDS(ON) PARAMETER Drain-source clamp voltage Drain current (DC) Total power dissipation Junction temperature Repetitive clamped turn off energy; Tj = 150˚C Drain-source on-state resistance; VGS = 5 V MIN.
40 TYP.
48 MAX.
UNIT 58 21 75 175 50 8...