Features • High Density, High Performance Electrically Erasable Complex Programmable Logic Device – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 68, 84, 100, 160-pins – 7.
5 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 125 MHz – Enhanced Routing Resources • Flexible Logic Macrocell – D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic utilization by burying a register within a COM output • Advanced Power Management Features – Automatic 100 µA Stand-By for “Z” Version (Max.
) – Pin-Cont...

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