April 2004 AS7C3256A ® 3.
3V 32K X 8 CMOS SRAM (Common I/O) Features • Pin compatible with AS7C3256 • Industrial and commercial temperature options • Organization: 32,768 words × 8 bits • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Very low power consumption: ACTIVE - 180mW max @ 10 ns • Very low power consumption: STANDBY - 7.
2 mW max CMOS I/O • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.
4 mm TSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Row decoder Sense amp AS7C3256A Logic block diagram VCC GND A0 A1 A2 A3 A4 A5 A6 A7 Input bu...

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