Part Number
|
BR02 |
Manufacturer
|
AMI |
Description
|
CMOS Gate Array |
Published
|
Mar 12, 2018 |
Detailed Description
|
Core Logic
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Description BR0x is a family of non-inverting bus receivers with ...
|
Datasheet
|
BR02
|
Overview
Core Logic
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Description BR0x is a family of non-inverting bus receivers with a single output to be used as the output of tristate busses.
Logic Symbol
Truth Table
BR0x
AQ AQ
AQ LL HH
HDL Syntax Verilog BR0x inst_name (Q, A); VHDL.
.
inst_name: BR0x port map (Q, A);
Pin Loading Pin Name A
BR02 1.
0
Equivalent Loads BR04 2.
1
BR06 2.
1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
BR02
2.
0
TBD
3.
8
BR04
3.
0
TBD
7.
6
BR06
4.
0
TBD
10.
8
a.
See page 2-15 for power equation.
3-41
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