Part Number
|
DF401 |
Manufacturer
|
AMI |
Description
|
CMOS Gate Array |
Published
|
Mar 12, 2018 |
Detailed Description
|
')[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description
DF40x is a family of static, master-slave, multiplexed scan D fl...
|
Datasheet
|
DF401
|
Overview
')[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description
DF40x is a family of static, master-slave, multiplexed scan D flip-flops.
SET is asynchronous and active low.
Outputs are buffered and change state on the rising edge of the clock.
Logic Symbol DF40x
DS C SD SE
Q Q
Truth Table C D SD SE SN Q QN ↑HX LHHL ↑LXLHLH ↑ XHHHH L ↑X LHHLH XXXXLHL L X X X H NC NC NC = No Change
Core Logic
HDL Syntax Verilog .
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DF40x inst_name (Q, QN, C, D, SD, SE, SN); VHDL.
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inst_name: DF40x port map (Q, QN, C, D, SD, SE, SN);
Pin Loading
Pin Name
C D SD SE SN
DF401 1.
0 1.
0 1.
0 2.
1 2.
1
Equivalent Loads
DF402
DF404
1.
0 1.
0
1.
0 1.
0
1.
0 1.
0
2.
1 2.
2
2.
1 3.
1
DF40...
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