Core Logic '/[ $0,+*  PLFURQ &026 *DWH $UUD\ Description DL64x is a family of transparent, buffered D latches with active low gate transparency.
RESET is active low.
Logic Symbol Truth Table DL64x DQ G Q R RN D GN Q QN HL L LH HH L H L H X H NC NC LXXLH NC = No Change HDL Syntax Verilog .
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DL64x inst_name (Q, QN, D, GN); VHDL.
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inst_name: DL64x port map (Q, QN, D, GN); Pin Loading Pin Name D GN RN DL641 1.
0 1.
0 1.
0 Equivalent Loads DL642 DL644 1.
0 1.
0 1.
0 1.
0 1.
0 1.
0 DL646 1.
0 1.
0 1.
0 Size And Power Characteristics Cell DL641 DL642 Equivalent Gates 5.
0 7.
0 Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TB...

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