HEF4020B 14-stage binary counter Rev.
11 — 7 December 2021 Product data sheet 1.
General description The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.
2.
Features and benefits • Wide supply voltage range from 3.
0 V to 15.
0 V • CMOS ...

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