Part Number
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M14D128168A |
Manufacturer
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ESMT |
Description
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DDR-II SDRAM |
Published
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Sep 20, 2018 |
Detailed Description
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ESMT
DDR II SDRAM
M14D128168A (2Y)
2M x 16 Bit x 4 Banks DDR II SDRAM
Features
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ ...
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Datasheet
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M14D128168A
|
Overview
ESMT
DDR II SDRAM
M14D128168A (2Y)
2M x 16 Bit x 4 Banks DDR II SDRAM
Features
JEDEC Standard VDD = 1.
8V ± 0.
1V, VDDQ = 1.
8V ± 0.
1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition 1KB page size - Row address: A0 to A11 - Column address: A0 to A8 Quad bank operation CAS Latency : 3, 4, 5, 6, 7 Additive Latency: 0, 1, 2, 3, 4, 5, 6 Burst Type : Sequential and Interleave Burst Length : 4, 8 All inputs except data & DM are sampled at the rising ...
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