Part Number
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M15T2G8256A |
Manufacturer
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ESMT |
Description
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DDR3 SDRAM |
Published
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Sep 20, 2018 |
Detailed Description
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ESMT
DDR3(L) SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VD...
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Datasheet
|
M15T2G8256A
|
Overview
ESMT
DDR3(L) SDRAM
(Preliminary)
Feature
Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.
5V(±0.
075V) ˗ SSTL_135: VDD/VDDQ = 1.
35V(-0.
067V/+0.
1V) JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM
Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes
Power Saving Mode ˗ Power Down Mode
Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy
via external ZQ pad (240 ohm ± 1%)
Note: 1.
Only Support prime DQ’s feedback for each byte lane.
M15T2G8256A (2L)
32M x 8 Bit...
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