ESMT SDRAM FEATURES JEDEC standard 3.
3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) - 15.
6 µ s refresh interval M12L64164A (2C) 1M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq.
Package Comments M12L64164A-5TG2C 200MHz 54 TSOP II Pb-free M12L64164A-6TG2C 166MHz 54 TSOP II Pb-free M12L64164A-7TG2C M12L64164A-5BG2C M12L64164A-6BG2C M12L64164A-7BG2C 143MHz...

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