Low Skew 1 to 4 Clock Buffer 553S DATASHEET Description The 553S is a low skew, single input to four output, clock buffer.
The 553S has best in class additive phase Jitter of sub 50 fsec.
IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features • Low additive phase jitter RMS: 50fs • Extremely low skew outputs (50ps) • Low cost clock buffer • Packaged in 8-SOIC and small 8-DFN package, Pb-free • Input/Output clock frequency up to 200MHz • Ideal for networking clocks • Operating voltages: 1.
8V to 3.
3V • Output Enable mode tri-states outputs • Advanced, low power CMOS process • Exte...

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