DATASHEET 1.
35V/1.
5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882HLB Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.
35V and 1.
5V VDD operation.
All inputs are 1.
35V and 1.
5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS.
All outputs are 1.
35V and 1.
5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output.
The clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn and QnODTn are designed with a different strength and skew to compensate for different loading ...

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