ESMT DDR III SDRAM Feature z 1.
5V ± 0.
075V (JEDEC Standard Power Supply) z Programmable CAS　Latency: 5, 6, 7, 8, 9, 10 and 11 z 8 Internal memory banks (BA0- BA2) z Differential clock input (CK, CK ) z CAS WRITE Latency (CWL): 5,6,7,8,9 z POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock z Programmable Sequential / Interleave Burst Type z Through ZQ pin (RZQ:240 ohm±1%) z Programmable Burst Length: 4, 8 M15F2G16128A (2F) 16M x 16 Bit x 8 Banks DDR III SDRAM z 8n-bit prefetch architecture z Output Driver Impedance Control z Differential bidirectional data strobe z Internal(self) calibration:Internal self calibration z OCD Calibration z Dynamic ODT (Rtt_Nom & Rtt_WR)...

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