74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev.
6 — 26 May 2020 Product data sheet 1.
General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.
Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input.
A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input.
The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
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