74AHC594-Q100;
74AHCT594-Q100
8-bit shift register with output register
Rev.
4 — 7 July 2021
Product data sheet
1.
General description
The 74AHC594-Q100; 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power
Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7-A.
The 74AHC594-Q100; 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers.
A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks...