D EPIC™ (Enhanced-Performance Implanted CMOS ) 1-µm Process D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic DIPs (NT) 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 DB, DW, NT, OR PW PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4 1 2 3 4 5 6 7 8 9 10 11 12 24 1OE 23 1A1 22 1A2 21 1A3...

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