• Inputs Are TTL-Voltage Compatible • Contains Six D-Type Flip-Flops • Clock Enable Latched to Avoid False Clocking • Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise • EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs 74ACT11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS185A − AUGUST 1990 − REVISED APRIL 1993 DW OR N PACKAGE (TOP VIEW) 1Q 2Q 3Q GND GND GND GND 4Q 5Q 6Q 1 2 3 4 5 6 7 8...

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