ą • Eight Latches in a Single Package • 3-State Bus-Driving Inverting Outputs • Full Parallel Access for Loading • Buffered Control Inputs • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description 54ACT11533, 74ACT11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993 54ACT11533 .
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JT PACKAGE 7...

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