SN54CDC586 3.
3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUPUTS SGBS311A – FEBRUARY 1997 – REVISED JULY 2002 D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.
3-V VCC D Distributes One Clock Input to 12 Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input D Application for Synchronous DRAM, High-Speed Microprocessor D TTL-Compatible Inputs and Outputs D Outputs Drive Parallel 50-Ω Terminated Transmission Lines D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces P...

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