Part Number
|
EP1810 |
Manufacturer
|
Altera |
Description
|
EPLD |
Published
|
Nov 11, 2019 |
Detailed Description
|
May 1999, ver. 5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900...
|
Datasheet
|
EP1810
|
Overview
May 1999, ver.
5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates (see Table 1)
s Device erasure and reprogramming with non-volatile EPROM configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages
s Programmable security bit for protection of proprietary designs s 100% generically tested to provide 100% programming yield s Programmable registers providing D, T, JK, and SR flipflops with
individual clear an...
Similar Datasheet