Data sheet acquired from Harris Semiconductor SCHS134E February 1998 - Revised September 2003 CD54HC73, CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject (Dual J-K FlipFlop Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs .
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10 LSTTL Loads - Bus Driver Outputs .
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15 LSTTL Loads • Wide Operating Temperature Range .
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-55oC to 125oC • Balan...

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