R5F51305AGFN

R5F51305AGFK : CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers  Basic instructions: 73 (variable-length instruction format)  DSP instructions: 9  Addressing modes: 10  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit  On-chip divider: 32-bit ÷ 32-bit → 32 bits  Barrel shifter: 32 bits Memory ROM  Capacity: 64 K/128 Kbytes  No-wait memory access  Programming/era.

R5F51305AGFK : Datasheet RX130 Group Renesas MCUs 32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory, R01DS0273EJ0300 Rev.3.00 Aug 09, 2018 up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply Features ■ 32-bit RX CPU core • Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) • Fast interrupt • CISC Harvard architecture with 5-stage pipeline • Variable-length instru.

R5F51305AGFL : CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers  Basic instructions: 73 (variable-length instruction format)  DSP instructions: 9  Addressing modes: 10  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit  On-chip divider: 32-bit ÷ 32-bit → 32 bits  Barrel shifter: 32 bits Memory ROM  Capacity: 64 K/128 Kbytes  No-wait memory access  Programming/era.

R5F51305AGFL : Datasheet RX130 Group Renesas MCUs 32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory, R01DS0273EJ0300 Rev.3.00 Aug 09, 2018 up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply Features ■ 32-bit RX CPU core • Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) • Fast interrupt • CISC Harvard architecture with 5-stage pipeline • Variable-length instru.

R5F51305AGFM : CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers  Basic instructions: 73 (variable-length instruction format)  DSP instructions: 9  Addressing modes: 10  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit  On-chip divider: 32-bit ÷ 32-bit → 32 bits  Barrel shifter: 32 bits Memory ROM  Capacity: 64 K/128 Kbytes  No-wait memory access  Programming/era.

R5F51305AGFM : Datasheet RX130 Group Renesas MCUs 32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory, R01DS0273EJ0300 Rev.3.00 Aug 09, 2018 up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply Features ■ 32-bit RX CPU core • Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) • Fast interrupt • CISC Harvard architecture with 5-stage pipeline • Variable-length instru.

R5F51305AGFN : CPU CPU  Maximum operating frequency: 32 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per clock cycle  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit registers  Basic instructions: 73 (variable-length instruction format)  DSP instructions: 9  Addressing modes: 10  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit  On-chip divider: 32-bit ÷ 32-bit → 32 bits  Barrel shifter: 32 bits Memory ROM  Capacity: 64 K/128 Kbytes  No-wait memory access  Programming/era.