SN74HCT377

SN74HCT373 : These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’HCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low,the Q outputs are latched at the levels that were set up at the D inputs. PART NUMBER Device Information PACKAGE(1) BODY SIZE (NOM) SN74HCT373DW SOIC (20) 12.80 mm × 7.50 mm SN74HCT373N PDIP (20) 25.40 mm × 6.35 mm SN74HCT373NSR SO (20) 15.00 mm × 5.30.

SN74HCT374 : These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ’HCT374 devices are edgetriggered D-type flip-flops. On the positive transition ofthe clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines si.

SN74HCT377N : ordering information These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN. ORDERING INFORM.