Part Number
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74F112 |
Manufacturer
|
Texas Instruments |
Description
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DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP |
Published
|
Nov 23, 2020 |
Detailed Description
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SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER...
|
Datasheet
|
74F112
|
Overview
SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
• Package Options Include Plastic
Small-Outline Packages and Standard Plastic 300-mil DIPs
description
The SN74F112 contains two independent J-K negative-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not directly related to the rise time...
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