74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev.
02 — 12 June 2008
Product data sheet
1.
General description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power
Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.
A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
The E input is only ...