HD74LS30P

HD74LS30 : Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + – 0.20 1.27 *0.4.

HD74LS30 : HD74LS30 8-input Positive NAND Gate Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS30P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS30FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74LS30RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. Pin Arrangement REJ03D0404–0200 Rev.2.00 Feb.18.2005 Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) A1 B2 C3 D4 E5 F6 GND 7 14 VCC 13 NC 12 H 11 G 10 NC 9 NC 8Y (Top view) Rev.2.00, Feb.18.2005, page 1 of 5 HD74LS30 Circuit Schematic Inputs A B C D E F G H 17k 8k VCC .