Si5365
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Features
Not recommended for new
Five clock outputs with selectable
designs.
For alternatives, see the signal format (LVPECL, LVDS,
Si533x family of products.
CML, CMOS)
Selectable output frequencies Support for ITU G.
709 FEC ratios ranging from 19.
44 to 1050 MHz (255/238, 255/237, 255/236)
Low jitter clock outputs w/jitter LOS alarm outputs
generation as low as 0.
6 ps rms Pin-programmable settings
(50 kHz–80 MHz)
On-chip voltage
regulator for
Integrated loop filter with
1.
8 ±5%, 2.
5 V ±10%, or
selectable loop bandwidth
3.
3 V ±10% operation
(150 kHz to 1.
3 MHz)
Small size: 14 x 14 mm 100-pin
Four cloc...