54ACT16833, 74ACT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCAS166A – JUNE 1990 – REVISED APRIL 1996 D Members of the Texas Instruments Widebus ™ Family D Inputs Are TTL-Voltage Compatible D Parity Error Flag With Parity Generator/Checker D Register for Storage of the Parity Error Flag D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25...

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